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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14046B Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators, a voltage-controlled oscillator (VCO), source follower, and zener diode. The comparators have two common signal inputs, PCAin and PCBin. Input PCAin can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1out, and maintains 90 phase shift at the center frequency between PCAin and PCBin signals (both at 50% duty cycle). Phase comparator 2 (with leading edge sensing logic) provides digital error signals, PC2 out and LD, and maintains a 0 phase shift between PCA in and PCB in signals (duty cycle is immaterial). The linear VCO produces an output signal VCOout whose frequency is determined by the voltage of input VCO in and the capacitor and resistors connected to pins C1A, C1B, R1, and R2. The source-follower output SFout with an external resistor is used where the VCO in signal is needed but no loading can be tolerated. The inhibit input Inh, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode can be used to assist in power supply regulation. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and motor speed control. * * * * * * Buffered Outputs Compatible with MHTL and Low-Power TTL Diode Protection on All Inputs Supply Voltage Range = 3.0 to 18 V Pin-for-Pin Replacement for CD4046B Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited Phase Comparator 2 switches on Rising Edges and is not Duty Cycle Limited
L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648
DW SUFFIX SOIC CASE 751G
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
PIN ASSIGNMENT
LD PC1out PCBin VCOout INH C1A C1B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD ZENER PCAin PC2out R2 R1 SFout VCOin
BLOCK DIAGRAM
SELF BIAS CIRCUIT PHASE COMPARATOR 1 PHASE COMPARATOR 2 VOLTAGE CONTROLLED OSCILLATOR (VCO) SOURCE FOLLOWER VSS
VSS
PCAin 14 PCBin 3 VCOin 9 VDD = PIN 16 VSS = PIN 8 INH 5
2 PC1out 13 PC2out 1 LD 4 11 12 6 7 VCOout R1 R2 C1A C1B
10 SFout 15 ZENER
10/97
(c) Motorola, Inc. 1997CMOS LOGIC DATA MOTOROLA
1
REV 4
MC14046B 1
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Rating Symbol VDD Vin Iin DC Supply Voltage Value Unit Vdc Vdc - 0.5 to + 18 Input Voltage, All Inputs - 0.5 to VDD + 0.5 10 500 DC Input Current, per Pin mAdc mW Power Dissipation, per Package Operating Temperature Range Storage Temperature Range PD TA - 55 to + 125 - 65 to + 150
_C _C
Tstg
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Ch ii Symbol S bl VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 15 -- Min -- -- --
- 55_C
25_C Typ 0 0 0
125_C
Max
Min -- -- --
Max
Min -- -- --
Max
Unit Ui Vdc
Output Voltage Vin = VDD or 0
"0" Level
0.05 0.05 0.05 -- -- --
0.05 0.05 0.05 -- -- --
0.05 0.05 0.05 -- -- --
"1" Level
VOH
Vin = 0 or VDD
4.95 9.95 14.95 -- -- --
4.95 9.95 14.95 -- -- --
5.0 10 15
4.95 9.95 14.95 -- -- --
Vdc
Input Voltage # (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)
"0" Level
VIL
Vdc
1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- --
2.25 4.50 6.75 2.75 5.50 8.25
1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- --
1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- --
"1" Level
VIH
3.5 7.0 11
3.5 7.0 11
3.5 7.0 11
Vdc
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
IOH
mAdc
Source
- 1.2 - 0.25 - 0.62 - 1.8 0.64 1.6 4.2 -- -- -- -- --
- 1.0 - 0.2 - 0.5 - 1.5 0.51 1.3 3.4 -- -- -- -- --
- 1.7 - 0.36 - 0.9 - 3.5 0.88 2.25 8.8
- 0.7 - 0.14 - 0.35 - 1.1 0.36 0.9 2.4 -- -- -- -- --
Sink
IOL
mAdc
Input Current
Input Capacitance
Iin Cin
0.1 -- 5.0 10 20
0.00001 5.0 0.005 0.010 0.015
0.1 7.5 5.0 10 20
1.0 -- 150 300 600
Adc pF Adc
Quiescent Current (Per Package) Inh = PCAin = VDD, Zener = VCOin = 0 V, PCBin = VDD or 0 V, Iout = 0 A Total Supply Current (Inh = "0", fo = 10 kHz, CL = 50 pF, R1 = 1.0 M, R2 = RSF = , and 50% Duty Cycle)
IDD
5.0 10 15 5.0 10 15
IT
R
IT = (1.46 A/kHz) f + IDD IT = (2.91 A/kHz) f + IDD IT = (4.37 A/kHz) f + IDD
mAdc
#Noise immunity specified for worst-case input combination. Noise Margin for both "1" and "0" level = 1.0 Vdc min @ VDD = 5.0 Vdc 2.0 Vdc min @ VDD = 10 Vdc 2.5 Vdc min @ VDD = 15 Vdc To Calculate Total Current in General: VCOin - 1.65 VDD - 1.35 3/4 VCOin - 1.65 3/4 IT 2.2 x VDD + 1 x 10-3 (CL + 9) VDD f + + 1.6 x + RSF R1 R2
[
1 x 10-1 VDD2
100% Duty Cycle of PCAin 100
+ IQ
where: IT in A, CL in pF, VCOin, VDD in Vdc, f in kHz, and R1, R2, RSF in M, CL on VCOout.
MC14046B 2
MOTOROLA CMOS LOGIC DATA
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* The formula given is for the typical characteristics only. ZENER DIODE SOURCE-FOLLOWER VOLTAGE CONTROLLED OSCILLATOR (VCO) PHASE COMPARATORS 1 and 2
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25C)
Dynamic Resistance (Iz = 1.0 mA)
Zener Voltage (Iz = 50 A)
Linearity (VCOin = 2.5 V 0.3 V, RSF > 50 k) (VCOin = 5.0 V 2.5 V, RSF > 50 k) (VCOin = 7.5 V 5.0 V, RSF > 50 k)
Offset Voltage (VCOin minus SFout, RSF > 500 k)
Input Resistance -- VCOin
Output Duty Cycle
Linearity (R2 = ) (VCOin = 2.5 V 0.3 V, R1 > 10 k) (VCOin = 5.0 V 2.5 V, R1 > 400 k) (VCOin = 7.5 V 5.0 V, R1 1000 k)
Temperature -- Frequency Stability (R2 = )
Maximum Frequency (VCOin = VDD, C1 = 50 pF R1 = 5.0 k, and R2 = )
DC Coupled -- PCAin, PCBin
Minimum Input Sensitivity AC Coupled -- PCAin C series = 1000 pF, f = 50 kHz
Input Resistance -- PCAin
Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns
Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns
MOTOROLA CMOS LOGIC DATA
-- PCBin Characteristic Ch ii Symbol S bl fmax tTHL tTLH Rin Rin Rin Vin RZ VZ -- -- -- -- -- -- 5 to 15 5 to 15 VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 15 -- -- Minimum Device 150 150 6.7 0.5 1.0 1.4 1.0 0.2 0.1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- See Noise Immunity Typical Til 0.12 0.04 0.015 1500 1500 1.65 1.65 1.65 100 200 400 700 100 50 37 180 90 65 7.0 0.1 0.6 0.8 1.0 1.0 1.0 0.7 1.4 1.9 2.0 0.4 0.2 50 300 600 1050 175 75 55 350 150 110 7.3 2.2 2.2 2.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Maximum
Device
MC14046B 3
mV p-p Units Ui %/_C MHz M M M ns ns % % % V V
PHASE COMPARATOR 1
Input Stage 00 XX 11 PCAin PCBin 0 1 10 01
PC1out
PHASE COMPARATOR 2
Input Stage
XX 01
00 PCBin 10 11 10
00 01 11 01
00 10 11
PCAin
PC2out LD (Lock Detect) Refer to Waveforms in Figure 3.
0 0
3-State Output Disconnected 1
1 0
Figure 1. Phase Comparators State Diagrams
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Characteristic Using Phase Comparator 1 Using Phase Comparator 2 No signal on input PCAin. VCO in PLL system adjusts to center frequency (f0). VCO in PLL system adjusts to minimum frequency (fmin). Phase angle between PCAin and PCBin. Locks on harmonics of center frequency. Signal input noise rejection. 90 at center frequency (f0), approaching 0_ and 180 at ends of lock range (2fL) Yes Always 0_ in lock (positive rising edges). No High Low Lock frequency range (2fL). The frequency range of the input signal on which the loop will stay locked if it was initially in lock; 2fL = full VCO frequency range = fmax - fmin. Capture frequency range (2fC). The frequency range of the input signal on which the loop will lock if it was initially out of lock. Depends on low-pass filter characteristics (see Figure 3). fC fL
v
fC = fL
Center frequency (f0).
The frequency of VCOout, when VCOin = 1/2 VDD fmin = 1
VCO output frequency (f).
R2(C1 + 32 pF) 1
(VCO input = VSS)
Note: These equations are intended to be a design guide. Since calculated component values may be in error by as much as a factor of 4, laboratory experimentation may be required for fixed designs. Part to part frequency variation with identical passive components is typically less than 20%.
fmax =
R1(C1 + 32 pF)
+ fmin
(VCO input = VDD)
Where: 10K R1 1M 10K R2 1M 100pF C1 .01 F
vv vv vv
Figure 2. Design Information
MC14046B 4
MOTOROLA CMOS LOGIC DATA
9 VCOin PCAin @ FREQUENCY f PCBin 14 3 2 OR 13 PHASE COMPARATOR PC1out OR PC2out EXTERNAL LOW-PASS FILTER 9 11 R1 EXTERNAL /N COUNTER R2
SOURCE FOLLOWER
10
SFout RSF
12
VCO 6 CIA CI
4 7 CIB
VCOout @ FREQUENCY Nf = f
Typical Low-Pass Filters
(a) INPUT R3 OUTPUT C2 2fC (a) INPUT R3 OUTPUT R4 (R3 C2 Typically: R4 C2 6N + fmax - 2
[p
1
2 pfL R3 C2
) 3, 000W) C2 + 100NDf fmax2
pD
N
f - R4 C2
f = fmax - fmin NOTE: Sometimes R3 is split into two series resistors each R3 / 2. A capacitor CC is then placed from the midpoint to ground. The value for CC should be such that the corner frequency of this network does not significantly affect n. In Figure B, the ratio of R3 to R4 sets the damping, R4 (0.1)(R3) for optimum results.
^
LOW-PASS FILTER
Filter A Definitions: N = Total division ratio in feedback loop K = VDD/ for Phase Comparator 1 K = VDD/4 for Phase Comparator 2 2 p D fVCO KVCO VDD - 2 V 2 p fr for a typical design n (at phase detector input) 10 0.707 Filter B
wn +
+
KfKVCO NR3C2 Nw
wn +
KfKVCO NC2(R3 R4)
)
^
^
z + 2K K n f VCO
F(s)
+ R3C21S ) 1
) KfKN ) VCO R3C2S ) 1 F(s) + S(R3C2 ) R4C2) ) 1
(R3C2
z + 0.5 wn
Waveforms Phase Comparator 1
PCAin VDD VSS VOH PCBin PC1out VCOin VOL VOH VOL VOH VOL VCOin Note: for further information, see: (1) F. Gardner, "Phase-Lock Techniques", John Wiley and Son, New York, 1966. (2) G. S. Moschytz, "Miniature RC Filters Using Phase-Locked Loop", BSTJ, May, 1965. (3) Garth Nash, "Phase-Lock Loop Design Fundamentals", AN-535, Motorola Inc. (4) A. B. Przedpelski, "Phase-Locked Loop Design Articles", AR254, reprinted by Motorola Inc. PCBin LD PC2out PCAin
Phase Comparator 2
VDD VSS VOH VOL VOH VOL VOH VOL VOH VOL
Figure 3. General Phase-Locked Loop Connections and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14046B 5
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MC14046B 6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC WIDE PACKAGE CASE 751G-03 ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1
8
16X
B TA
S
B B
S
h X 45_
M
8X
0.25
E
0.25
M
A1
14X
e
SEATING PLANE
DIM A A1 B C D E e H h L
A
L
T
C
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Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps/ JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488
MOTOROLA CMOS LOGIC DATA
MC14046B MC14046B/D 7

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